library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY UART IS
PORT(
CLOCK_50_u: IN STD_LOGIC;
SW_u: IN STD_LOGIC_VECTOR(4 downto 0);
KEY_u: IN STD_LOGIC_VECTOR(3 downto 0);
LEDR_u:OUT STD_LOGIC_VECTOR(9 downto 0);
LEDG_u:OUT STD_LOGIC_VECTOR(4 downto 0);
UART_TXD_u:OUT STD_LOGIC;
UART_RXD_u:IN STD_LOGIC
);
END UART;
 
 
 
ARCHITECTURE MAIN OF UART IS
SIGNAL TX_DATA: STD_LOGIC_VECTOR(4  downto 0);
SIGNAL TX_START: STD_LOGIC:='0';
SIGNAL TX_BUSY: STD_LOGIC;
SIGNAL RX_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL RX_BUSY: STD_LOGIC;
----------------------------------------
COMPONENT TX
PORT(
CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
BUSY:OUT STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(4 downto 0);
TX_LINE:OUT STD_LOGIC
);
END COMPONENT TX;
----------------------------------------
COMPONENT RX
PORT(
CLK:IN STD_LOGIC;
RX_LINE:IN STD_LOGIC;
DATA:OUT STD_LOGIC_VECTOR(7 downto 0);
BUSY:OUT STD_LOGIC
);
END COMPONENT RX;
------------------------------------------------------
BEGIN
C1: TX PORT MAP (CLOCK_50_u,TX_START,TX_BUSY,TX_DATA,UART_TXD_u);
C2: RX PORT MAP (CLOCK_50_u,UART_RXD_u,RX_DATA,RX_BUSY);
 
 
PROCESS(RX_BUSY)
BEGIN
IF(RX_BUSY'EVENT AND RX_BUSY='0')THEN
LEDR_u(7 DOWNTO 0)<=RX_DATA;
END IF;
END PROCESS;
 
 
 
PROCESS(CLOCK_50_u)
BEGIN
IF(CLOCK_50_u'EVENT AND CLOCK_50_u='1')THEN
   IF(KEY_u(0)='0' AND TX_BUSY='0')THEN
           TX_DATA<=SW_u(4 DOWNTO 0);
                TX_START<='1';
                LEDG_u<=TX_DATA;
           ELSE
                TX_START<='0';
        END IF;
END IF;
END PROCESS;
END MAIN;